Modeling Custom Hardware in VHDL

This report focuses on models for describing Hardware at di erent re nement levels within High Level Synthesis ow: SFSMD, FSMD and FSM Controlling Datapath. Simple data interfaces are often needed in these models. The hardware description language VHDL is used and tested for implementing these models and interfaces. Problems inherent in the models as well as problems caused by VHDL are discussed. A model related main di culty is the one-cycle delay of data processing, when introducing a datapath. VHDL descriptions of abstract models (SFSMD) can become complicated. Templates for general problems, examples and VHDL guidelines are provided in this report to help to minimize design errors signi cantly.